Firmware Engineer

TalentPro Consulting

(Phoenix, Arizona)

Full Time

Job Posting Details

About TalentPro Consulting

TalentPro Consulting is a full service Technical recruiting firm that connects top-notch technical personnel with employers around the United States.

Summary

As a FPGA Developer, you will work with a team of local and overseas HDL developers to complete CPLD and FPGA designs, simulations, synthesis, floor-planning and lab integration.

Responsibilities

* Work with a team of FPGA designers to ensure efficient work, status, problem resolution and customer satisfaction.
* Provide training as required to ensure compliance with DO-254 and other industry standards and certification standards.
* Follow DO-254 Level A program planning documentation, and ensure CPLD/FPGA design team adheres to the plans.
* Capture and document the customer flowed down functional requirements, and develop and document the derived requirements for FPGAs.
* Design FPGA architectural diagrams, develop VHDL to implement the design critical functionality.
* Develop subfunctions and test benches.
* Perform engineering timing simulations and functional analysis.
* Interface with the V&V team and Quality Engineers to support the creation of the DO-254 required artifacts.
* Most critically, the ideal candidate will be able to prioritize multiple requests in a fast-paced environment with impeccable attention to detail and accuracy while maintaining a pleasant and "can do" attitude.
* The successful candidate must be willing to pitch in and do whatever is necessary to get the job done right.

Work with a team of FPGA designers to ensure efficient work, status, problem resolution and customer satisfaction.
Provide training as required to ensure compliance with DO-254 and other industry standards and certification standards.
Follow DO-254 Level A program planning documentation, and ensure CPLD/FPGA design team adheres to the plans.
Capture and document the customer flowed down functional requirements, and develop and document the derived requirements for FPGAs.
Design FPGA architectural diagrams, develop VHDL to implement the design critical functionality.
Develop subfunctions and test benches.
Perform engineering timing simulations and functional analysis.
Interface with the V&V team and Quality Engineers to support the creation of the DO-254 required artifacts.
Most critically, the ideal candidate will be able to prioritize multiple requests in a fast-paced environment with impeccable attention to detail and accuracy while maintaining a pleasant and "can do" attitude.
The successful candidate must be willing to pitch in and do whatever is necessary to get the job done right.

Ideal Candidate

* To be considered, responses must include information meeting EDUCATION and EXPERIENCE requirements.
* BS degree in Electrical Engineering or Computer Engineering; Computer Science is required.
* At least six (or four with Masters) years’ experience in VHDL or Verilog design for CPLDs or FPGAs in an Aerospace environment.
* Design or project leadership experience.
* In depth experienced simulating HDL and using Mentor Modelsim.
* Experience with Actel, Xilinx, FPGAs and development tools.
* Excellent FPGA lab integration and troubleshooting knowledge.
* Experience with timing closure techniques
* Experience of full development cycle (including system and block level testing)
* Strong understanding of software and hardware interaction
* Must display excellent teamwork, team leadership and problem solving skills.
* Must be a US Person.
* bility to design test benches.
* Experience with Mentor HDL Designer, Precision Synthesis, Questa and Req Tracer.
* Experience with DO-254 Level A design methodology for Complex Electronic Hardware.

To be considered, responses must include information meeting EDUCATION and EXPERIENCE requirements.
BS degree in Electrical Engineering or Computer Engineering; Computer Science is required.
At least six (or four with Masters) years’ experience in VHDL or Verilog design for CPLDs or FPGAs in an Aerospace environment.
Design or project leadership experience.
In depth experienced simulating HDL and using Mentor Modelsim.
Experience with Actel, Xilinx, FPGAs and development tools.
Excellent FPGA lab integration and troubleshooting knowledge.
Experience with timing closure techniques
Experience of full development cycle (including system and block level testing)
Strong understanding of software and hardware interaction
Must display excellent teamwork, team leadership and problem solving skills.
Must be a US Person.
bility to design test benches.
Experience with Mentor HDL Designer, Precision Synthesis, Questa and Req Tracer.
Experience with DO-254 Level A design methodology for Complex Electronic Hardware.