Packaging Technology Reliability Engineer, Senior Staff

Qualcomm (Nasdaq: QCOM) is the world leader in next generation mobile technologies. The company delivers innovative digital wireless communications products and services based on CDMA and other advanced technologies.

Qualcomm provides complete chipset solutions and integrated applications from the Launchpad suite of advanced silicon and packaging technologies such as lead free bumping, copper pillar, wafer level package, Cu wire bond, etc. The integrated solutions offer device manufacturers reduced bill-of-materials costs, time-to-market, and development time. Mobile handsets, netbooks, notebook PCs powered by QTI chipsets can offer more features while maintaining a small, sleek form-factor. This position requires hands-on experiences and skills to contribute to QTI businesses. Successful candidate will participate in cross functional teams supporting packaging technology development with emphases on reliability risk evaluation and mitigation for use with products designed and fabricated using advanced silicon technologies. Specific areas include packaging technology reliability evaluation (bill of materials, test structure designs and reliability test methodologies development), reliability risk assessments and mitigation. oSpecific projects include board level and microelectronic package reliability test methodology for board-package interaction reliability study/evaluation/analysis.

* Review/construct test structure design * Develop/define reliability test methodologies that take use condition and customer requirements into account, including stress conditions, pass/fail criteria, and statistics * Establish reliability test plan (resource, schedule) and drive reliability evaluation * Report reliability test results with recommendations * Document learning from packaging reliability evaluation and packaging technology benchmarking (from industry and symposia) * Support due diligence in the Packaging technology & supplier selection processes to include developing and supporting supplier reliability interface and technology investigations. Results will be published and communicated across relevant organizations within the business unit. Major focus will be establishing strong interdepartmental lines of communication to enhance the packaging/product development cycle, ensuring robust package/products which meet or exceed customer expectations. * Obtain/assess supplier packaging technology and analyze results for applicability to test chip and product oIdentify potential reliability/manufacturability issues, such as chip-package interaction/package-board interaction, to product and facilitate reliability mitigation plan development and implementation.

**Minimum Qualifications** * Minimum of 12 years experience in current/emerging CMOS, RFCMOS, Analog (such as Power Management, Power Amplifier) packaging technologies, with relevant package reliability knowledge **Preferred Qualifications** * Experience in mobile and high performance package & Reliability methodologies * Experience with the packaging materials and processes (solder balls, PCBs, underfills, mold compound, flux, etc.) Thermal mechanical stress analysis/simulation experience **Education Requirements** * Master's degree in Material Science, * Packaging Engineering or Mechanical * Engineering or Physical Science with Microelectronic packaging emphasis. Ph.D. preferred.