Staff ASIC Design Engineer

Founded in 1994, QLogic Corporation (Nasdaq QLGC) is a leading provider of data, server, and storage networking infrastructure solutions. QLogic is always at the forefront of networking technology innovation with a multi-faceted product portfolio of Fibre Channel, Ethernet, Fibre Channel over Ethernet (FCoE) and iSCSI networking solutions. Using a protocol-agnostic approach, QLogic provides end-to-end, integrated solutions that address the broad networking spectrum. The company’s leadership in t

We have an immediate need for a Staff ASIC Design Engineer in our corporate offices of Aliso Viejo, CA. In this critical design role the engineer will develop ASICs using industry standard tools and design methodologies.

Design specification, Verilog HDL coding, synthesis, functional and formal verification, timing analysis, and silicon debug. You will also work with the verification and firmware teams for ASIC verification using system simulation environment.

• BS or MS or equivalent degree in Electrical/Electronic Engineering, Computer Engineering or related discipline with 5-7 years of experience
• ASIC Macro/Micro architecture Design •Verilog RTL Coding
• Experience in front-end design of working silicon
• Familiarity with Verilog Simulation/Verification (Conventional, Assertion Based, Formal)
• RTL Synthesis, Equivalence Checking, Static Timing Analysis
• Design Debug and Validation •Design Documentation
• Knowledge of Data, telecom and storage networking is preferable
• Knowledge of bus protocols like I2C, SMBus and AHB is preferable
• Good communication and problem solving skills