Principal Physical Design Engineer

Founded in 1991, Broadcom’s mission is simple: Connecting everything®. Today, the company estimates that 99.98% of Internet traffic crosses at least one Broadcom chip – in the home, in the hand and across the network.

The Network Switch Group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multi-chip solutions to market over the last decade. This group works on physical implementation from netlist to gdsii of these complex chips with state of the arts cad tools and latest technology.This exciting opportunity position allows you to work on hierarchical block as well as top level physical design for internal as well as ASIC chips. Candidate will also work with the latest TSMC technology during the implementation of the physical blocks from netlist to gds2.

• Physical implementation of hierarchical blocks from netlist to gds2

• Floorplanning including memory and analog IPs. Interact with Design engineers to understand dataflow and place macros accordingly.

• Write custom scripts for optimized cell placements to meet timing/routability.

• Create good clock tree structure to minimize skew/insertion delays

• Analyze timing in P&R tool and optimize paths to meet timing. Discuss with DE if design changes needed

• Analyze routing. Cleanup shorts and drc's if needed.

• Run Primetime STA. Analyze reports and fix timing/noise/drv etc. to meet tapeout criteria

• Run calibre and analyze lvs/drc reports and fix violations.

• Implement eco if needed

• Support customers on the place and route, STA flow.

• BS or equivalent in Electrical Engineering with minimum 8-10 years of prior hands on experience on physical implementation

• Knowledge of verilog

• strong knowledge of STA .

• Good knowledge custom clock tree synthesis

• strong tcl/perl script writing skill

• Should possess strong verbal and written communication skill

• Hands on experience with Atop or cadence EDI is plus