Digital Backend Place and Route

Analog Solutions

(Chandler, Arizona)
Full Time
Job Posting Details
About Analog Solutions
Fowler Recruiting, LLC. dba Analog Solutions is an Analog Recruiter that assembles “Outstanding” Executive Technology Teams within the Analog and Mixed Signal Semiconductor and Nanotechnology world.
Responsibilities
- Chip and block level floor planning, analysis of floor plan options taking into account timing and area budgets - Net list generation, including synthesis, constraints, timing analysis and equivalence checking - Place and route, timing closure and power analysis - Physical verification * GDS (or OAS) are formats representing the micro chips' layout data. This data is transferred to the silicon foundry manufacturing the chip
Ideal Candidate
**Qualifications** * You should possess a University / University of applied sciences: master or bachelor degree in Electrical Engineering or Information Technology required. * Experience/first studies in physical design desired but not required * Software skills including Perl, Tcl, Unix and Linux appreciated * We expect a highly-motivated technical expert with good communication and presentation skills. Strong interests in problem solving and an attitude to convince people of own ideas as well as openness towards novel technical directions are mandatory. * The candidate should be capable of working in multi-disciplinary / site / cultural teams. **Key Skills** * The successful candidate should be willing to incorporate hands-on experience of industry standard RTL to GDSII development flow, methodologies and EDA tools, with a proven track record in delivering complete RTL to GDSII projects. **Technical skills to familiarize with are:** - Comprehensive knowledge to the complete digital P&R flow - Logic synthesis, constraints and STA/PTSI - Chip/block level floor planning and P&R - Clock Tree Synthesis and timing closure - Power planning, power sign-off and IR Drop Analysis - Crosstalk noise analysis, physical verification, LVS and DRC - DFT (Design For Test), MBIST (Memory Built-In-Self Test) , scan, coverage - Synopsys EDA tools spanning the RTL to GDSII considered desirable but not essential

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